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integrated silicon solution, inc. 1-800-379-4774 1 rev. 00b 08/09/2010 copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex - pected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances IS41C44002C is41lv44002c features ? extended data-out (edo) page mode access cycle ? ttl compatible inputs and outputs ? refresh interval: C 2,048 cycles/32 ms ? refresh mode: ras -only, cas -before-ras (cbr), and hidden ? single power supply: 5v 10% (IS41C44002C) 3.3v 10% (is41lv44002c) ? byte write and byte read operation via two cas ? industrial temperature range: -40c to +85c ? rohs compliant description the issi is41c/41lv44002c is 4,194,304 x 4-bit high-perfor - mance cmos dynamic random access memory. these devices offer an accelerated cycle access called edo page mode. edo page mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. these features make the is41c/41lv44002c ideally suited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. the is41c/41lv44002c is packaged in a 24/26-pin 300-mil tsop2 with jedec standard pinout. 4mx4 16mb dram with edo page mode advanced information august 2010 key timing parameters parameter -50 unit ras access time (t r a c ) 50 ns cas access time (t c a c ) 13 ns column address access time (t a a ) 25 ns edo page mode cycle time (t p c ) 20 ns read/write cycle time (t r c ) 84 ns 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 vdd i/o0 i/o1 we ras nc a10 a0 a1 a2 a3 vdd gnd i/o3 i/o2 cas oe a9 a8 a7 a6 a5 a4 gnd pin descriptions a0-a10 address inputs i/o0-3 data inputs/outputs we write enable oe output enable ras row address strobe cas column address strobe v d d power gnd ground nc no connection pin configuration : 24/26-pin tsop2
2 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c functional block diagram o e we cas cas we oe data i/o bus column decoders sense amplifiers memory array 4,194,304 x 4 row decoder data i/o buffers cas control logic we control logics oe control logic i/o0-i/o3 ras ras a0-a10 ras clock generator refresh counter address buffers truth table function ras cas we oe address t r /t c i/o standby h h x x x high-z read l l h l row/col d write: word (early write) l l l x row/col d read-write l l h l l h row/col d , d edo page-mode read 1st cycle: l h l h l row/col d 2nd cycle: l h l h l na/col d edo page-mode write 1st cycle: l h l l x row/col d 2nd cycle: l h l l x na/col d edo page-mode 1st cycle: l h l h l l h row/col d , d read-write 2nd cycle: l h l h l l h na/col d , d hidden refresh read l h l l h l row/col d write (1) l h l l l x row/col d -only refresh l h x x row/na high-z cbr refresh h l l x x x high-z note: 1. early write only.
integrated silicon solution, inc. 1-800-379-4774 3 rev. 00b 08/09/2010 IS41C44002C is41lv44002c functional description the is41c/41lv44002c is a cmos drams optimized for high-speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 11 address bits. these are entered 11 bits (a0-a10) at a time for the 2k refresh device. the row ad- dress is latched by the row address strobe (ras). the column address is latched by the column address strobe (cas ). ras is used to latch the frst nine bits and cas is used the latter ten bits. memory cycle a memory cycle is initiated by bringing ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t r a s time has expired. a new cycle must not be initiated until the minimum precharge time t r p , t c p has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time speci - fed by t a r . data out becomes valid only when t r a c , t a a , t c a c and t o e a are all satisfed. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we, whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs last. auto refresh cycle to retain data, 2,048 refresh cycles are required in each 32 ms period. there are two ways to refresh the memory: 1. by clocking each of the 2,048 row addresses (a0 through a10) with ras at least once every 32 ms. any read, write, read-modify-write or ras-only cycle refreshes the addressed row. 2. using a cas -before-ras refresh cycle. cas -before-ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before-ras refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. cas -before-ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. power-on after application of the v d d supply, an initial pause of 200 s is required followed by a minimum of eight initializa - tion cycles (any combination of cycles containing a ras signal). during power-on, it is recommended that ras track with v d d or be held at a valid v i h to avoid current surges.
4 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 v d d supply voltage 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 i o u t output current 50 ma p d power dissipation 1 w t a operating temperature -40 to +85 c t s t g storage temperature C55 to +125 c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd.) symbol parameter test condition min. typ. max. unit v d d supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v i h input high voltage 5v 2.0 v d d + 1.0 v 3.3v 2.0 v d d + 0.3 v i l input low voltage 5v C1.0 0.8 v 3.3v C0.3 0.8 i i l input leakage current any input 0v v i n v d d C5 5 a other inputs not under test = 0v i i o output leakage current output is disabled (hi-z) C5 5 a 0v v o u t v d d v o h output high voltage level i o h = C5.0 ma 5v 2.4 v i o h = C2.0 ma 3.3v 2.4 v o l output low voltage level i o l = 4.2 ma 5v 0.4 v i o l = 2 ma 3.3v 0.4 t a commercial ambient temperature 0 +70 c industrial ambient temperature -40 +85 capacitance (1,2) symbol parameter max. unit c i n 1 input capacitance: a0-a10 5 pf c i n 2 input capacitance: ras, cas, we, oe 7 pf c i o data input/output capacitance: i/o0-i/o3 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz.
integrated silicon solution, inc. 1-800-379-4774 5 rev. 00b 08/09/2010 IS41C44002C is41lv44002c electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition v d d /speed min. max. unit i d d 1 standby current: ttl ras, cas v i h c o m . 5v 2 ma 3.3v 2 i n d . 5v 3 3.3v 2 i d d 2 standby current: cmos ras, cas v d d C 0.2v 5v 1 ma 3.3v 0.5 i d d 3 operating current: ras, cas, -50 120 ma random read/write (2,3,4) address cycling, t r c = t r c (min.) average power supply current i d d 4 operating current: ras = v i l , cas, -50 90 ma edo page mode (2,3,4) cycling t p c = t p c (min.) average power supply current i d d 5 refresh current: ras cycling, cas v i h -50 120 ma ras-only (2,3) t r c = t r c (min.) average power supply current i d d 6 refresh current: ras, cas cycling -50 120 ma cbr (2,3,5) t r c = t r c (min.) average power supply current notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles (ras-only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t r e f refresh requirement is exceeded. 2. dependent on cycle rates. 3. specifed values are obtained with minimum cycle time and the output open. 4. column-address is changed once each edo page cycle. 5. enables on-chip refresh and address counters.
6 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 symbol parameter min. max. units t r c random read or write cycle time 84 ns t r a c access time from ras (6, 7) 50 ns t c a c access time from cas (6, 8, 15) 13 ns t a a access time from column-address (6) 25 ns t r a s ras pulse width 50 10k ns t r p ras precharge time 30 ns t c a s cas pulse width (23) 8 10k ns t c p cas precharge time (9) 9 ns t c s h cas hold time (21) 38 ns t r c d ras to cas delay time (10, 20) 12 37 ns t a s r row-address setup time 0 ns t r a h row-address hold time 8 ns t a s c column-address setup time (20) 0 ns t c a h column-address hold time (20) 8 ns t a r column-address hold time 30 ns (referenced to ras) t r a d ras to column-address delay time (11) 10 25 ns t r a l column-address to ras lead time 25 ns t r p c ras to cas precharge time 5 ns t r s h ras hold time 8 ns t r h c p ras hold time from cas precharge 30 ns t c l z cas to output in low-z (15, 24) 0 ns t c r p cas to ras precharge time (21) 5 ns t o d output disable time (19, 24) 3 15 ns t o e output enable time (15, 16) 12 ns t o e d output enable data delay (write) 12 ns t o e h c oe high hold time from cas high 5 ns t o e p oe high pulse width 10 ns t o e s oe low to cas high setup time 5 ns t r c s read command setup time (17, 20) 0 ns t r r h read command hold time 0 ns (referenced to ras) (12) t r c h read command hold time 0 ns (referenced to cas) (12, 17, 21) t w c h write command hold time (17) 8 ns t w c r write command hold time 40 ns (referenced to ras) (17) t w p write command pulse width (17) 8 ns t w p z we pulse widths to disable outputs 7 ns
integrated silicon solution, inc. 1-800-379-4774 7 rev. 00b 08/09/2010 IS41C44002C is41lv44002c ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 symbol parameter min. max. units t r w l write command to ras lead time (17) 13 ns t c w l write command to cas lead time (17, 21) 8 ns t w c s write command setup time (14, 17, 20) 0 ns t d h r data-in hold time (referenced to ras ) 39 ns t a c h column-address setup time to cas 15 ns precharge during write cycle t o e h oe hold time from we during 8 ns read-modify-write cycle (18) t d s data-in setup time (15, 22) 0 ns t d h data-in hold time (15, 22) 8 ns t r w c read-modify-write cycle time 108 ns t r w d ras to we delay time during 64 ns read-modify-write cycle (14) t c w d cas to we delay time (14, 20) 26 ns t a w d column-address to we delay time (14) 39 ns t p c edo page mode read or write 20 ns cycle time t r a s p ras pulse width in edo page mode 50 100k ns t c p a access time from cas precharge (15) 30 ns t p r w c edo page mode read-write 56 ns cycle time t c o h data output hold after cas low 5 ns t o f f output buffer turn-off delay from 0 12 ns cas or ras (13,15,19, 24) t w h z output disable delay from we 3 10 ns t c s r cas setup time (cbr refresh) (20, 25) 5 ns t c h r cas hold time (cbr refresh) ( 21, 25) 8 ns t o r d oe setup time prior to ras during 0 ns hidden refresh cycle t r e f auto refresh period 2,048 cycles 32 ms t t transition time (rise or fall) (2, 3) 1 50 ns ac test conditions output load: two ttl loads and 50 pf (v d d = 5.0v 10%) one ttl load and 50 pf (v d d = 3.3v 10%) input timing reference levels: v i h = 2.0v, v i l = 0.8v (v d d = 5.0v 10%); v i h = 2.0v, v i l = 0.8v (v d d = 3.3v 10%) output timing reference levels: v o h = 2.4v, v o l = 0.4v (v d d = 5v 10%, 3.3v 10%)
8 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle (ras-only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t r e f refresh requirement is exceeded. 2. v i h (min) and v i l (max) are reference levels for measuring timing of input signals. transition times, are measured between v i h and v i l (or between v i l and v i h ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specifcation, all input signals must transit between v i h and v i l (or between v i l and v i h ) in a monotonic manner. 4. if cas and ras = v i h , data output is high-z. 5. if cas = v i l , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t r c d t r c d (max). if t r c d is greater than the maximum recommended value shown in this table, t r a c will increase by the amount that t r c d exceeds the value shown. 8. assumes that t r c d t r c d (max). 9. if cas is low at the falling edge of ras, data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t c p . 10. operation with the t r c d (max) limit ensures that t r a c (max) can be met. t r c d (max) is specifed as a reference point only; if t r c d is greater than the specifed t r c d (max) limit, access time is controlled exclusively by t c a c . 11. operation within the t r a d (max) limit ensures that t r c d (max) can be met. t r a d (max) is specifed as a reference point only; if t r a d is greater than the specifed t r a d (max) limit, access time is controlled exclusively by t a a . 12. either t r c h or t r r h must be satisfed for a read cycle. 13. t o f f (max) defnes the time at which the output achieves the open circuit condition; it is not a reference to v o h or v o l . 14. t w c s , t r w d , t a w d and t c w d are restrictive operating parameters in late write and read-modify-write cycle only. if t w c s t w c s (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t r w d t r w d (min), t a w d t a w d (min) and t c w d t c w d (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v i h ) is indeterminate. oe held high and we taken low after cas goes low result in a late write (oe-controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input. 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defned as we going low. 18. late write and read-modify-write cycles must have both t o d and t o e h met (oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t o e h is met. 19. the i/os are in open during read cycles once t o d or t o f f occur. 20. determined by falling edge of cas. 21. determined by rising edge of cas. 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read- modify-write cycles. 23. cas must meet minimum pulse width. 24. the 3 ns minimum is a parameter guaranteed by design.
integrated silicon solution, inc. 1-800-379-4774 9 rev. 00b 08/09/2010 IS41C44002C is41lv44002c read cycle note: 1. t o f f is referenced from rising edge of ras or cas , whichever occurs last. t ras t rc t rp t ar t cah t asc t rad t ral oe i/o we address cas ras row column row open open valid data t csh t cas t rsh t crp t clch t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clc t oes t oe t od dont care
10 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c early write cycle (oe = don't care) t ras t rc t rp t ar t cah t asc t rad t ral t ach i/o we address cas ras row column row t csh t cas t rsh t crp t clch t rcd t rah t asr t cwl t wcr t wch t rwl t wp t wcs t dh t ds t dhr valid data dont care
integrated silicon solution, inc. 1-800-379-4774 11 rev. 00b 08/09/2010 IS41C44002C is41lv44002c read write cycle (late write and read-modify-write cycles) t ras t rwc t rp t ar t cah t asc t rad t ral t ach we oe address cas ras row column row t csh t cas t rsh t crp t clch t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in dont care
12 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c edo-page-mode read cycle note: 1. t p c can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas. both measurements must meet the t p c specifcations. t rasp t rp address cas ras row row t cas, t clch t crp t rcd t csh t cp t cas, t clch t cah t cas, t clch t ral t rsh t cp t cp t pc (1) t asr t rah t rad t ar column column t cah t cah column t asc t asc oe i/o we open ope n valid data t aa t aa t cpa t cac t cac t rac t coh t clz t oep t oe t oes t oes t od t oe t oehc valid data t rch t rrh t aa t cpa t cac t off t clz valid data t od t asc t rcs dont care
integrated silicon solution, inc. 1-800-379-4774 13 rev. 00b 08/09/2010 IS41C44002C is41lv44002c edo-page-mode early-write cycle t rasp t rp address cas ras row row t cas, t clch t crp t rcd t csh t cp t cas, t clch t cah t cas, t clch t ral t rsh t cp t cp t pc t asr t rah t rad t ar t ach column column t ach t ach t cah t cah column t asc t asc oe i/o we valid data t asc t wcs t wch t cwl t wp t wcs t wch t cwl t wp t ds t dh t dhr t wcr t wcs t wch t cwl t wp valid data t ds t dh valid data t ds t rwl t dh dont care
14 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c edo-page-mode read-write cycle (late write and read-modify write cycles) note: 1. t p c can be measured from falling edge of cas to falling edge of cas , or from rising edge of cas to rising edge of cas. both measurements must meet the t p c specifcations. t rasp t rp address cas ras row row t crp t rcd t csh t cp t cah t cas, t clch t ral t rsh t cp t cp t rah t rad t ar t asr column column t cah t cah column t asc t asc t cas, t clch t cas, t clch oe i/o we t asc t rwd t rcs t cwl t wp t awd t cwd t dh t ds t cac t clz t awd t cwd t cwl t wp t awd t cwd t cwl t rwl t wp open open d in d out t oe t oe t oe t od t oeh t od t od t dh t ds t cpa t aa t cac t clz d in d out t dh t ds t cac t clz d in d out t cpa t aa t rac t aa t pc / t prwc (1) dont care
integrated silicon solution, inc. 1-800-379-4774 15 rev. 00b 08/09/2010 IS41C44002C is41lv44002c edo-page-mode read-early-write cycle (pseudo read-modify write) t rasp t rp address cas ras row row t crp t rcd t pc t csh t cp t cah t cas t ral t rsh t cp t cp t ach t rah t rad t ar t asr column (a) column (n) t cah t cah column (b) t asc t asc t cas t cas oe i/o we t asc t cac t rch t dh open open valid data (a ) t oe t wcs t cac t coh d in t cpa t wch t rac t aa t pc valid data (b ) t whz t ds t rcs t aa dont care
16 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c ac waveforms read cycle (with we-controlled disable) ras -only refresh cycle (oe, we = don't care) t ar t cah t asc t asc t rad oe i/o we address cas ras row column open open valid data t csh t cas t crp t rcd t cp t rah t asr t rch t rcs t rcs t aa t cac t whz t rac t clz t clz t oe t od column t ras t rc t rp i/o address cas ras row row open t crp t rah t asr t rpc dont care dont care
integrated silicon solution, inc. 1-800-379-4774 17 rev. 00b 08/09/2010 IS41C44002C is41lv44002c hidden refresh cycle (1) (we = high; oe = low) cbr refresh cycle (addresses; we, oe = don't care) notes: 1. a hidden refresh may also be performed after a write cycle. in this case, we = low and oe = high. 2. t o f f is referenced from rising edge of ras or cas , whichever occurs last. t ras t ras t rp t rp i/o cas ras open t cp t rpc t csr t chr t rpc t csr t chr t ras t ras t rp cas ras t crp t rcd t rsh t chr t ar t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od dont care dont care
18 integrated silicon solution, inc. 1-800-379-4774 rev. 00b 08/09/2010 IS41C44002C is41lv44002c ordering information: 3.3v industrial range: -40c to +85c speed (ns) order part no. refresh package 50 is41lv44002c-50ctgi 2k 300-mil tsop-ii, cu leadframe plated with matte snbi ordering information: 5v industrial range: -40c to +85c speed (ns) order part no. refresh package 50 IS41C44002C-50ctgi 2k 300-mil tsop-ii, cu leadframe plated with matte snbi notes: 1. part number with tli or ctgi are lead-free, and rohs compliant. 2. for the "g" option, bi is 3% or less of snbi plating.
integrated silicon solution, inc. 1-800-379-4774 19 rev. 00b 08/09/2010 IS41C44002C is41lv44002c 3. dimension b does not include dambar protrusion/intrusion. 4. reference document : jedec spec. ms-025 , a 1. controlling dimension : mm 2. dimension d and e1 do not include mold protrusion. note : 07/07/2008 package outline

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